R8CSLASH2G datasheet(209/344 Pages) RENESAS

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R8C/2G Group

17. Timers

Rev.1.00

Apr 04, 2008

Page 189 of 318

REJ09B0387-0100

Figure 17.34

TRECSR Register in Real-Time Clock Mode

Figure 17.35

TREOPR Register in Real-Time Clock Mode

Timer RE Count Source Select Register

Symbol

Address

After Reset

TRECSR

011Eh

00001000b

Bit Symbol

Bit Name

Function

NOTE:

b3 b2

RCS3

b1 b0

RCS0

b7 b6 b5 b4

RCS1

Count source select bits

Set to 00b in real-time clock mode.

4-bit counter select bit

Set to 0 in real-time clock mode.

Write to bits RCS4 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).

RCS2

—

(b7)

—

Real-time clock mode select bit

Set to 1 in real-time clock mode.

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

RCS6

RCS5

RCS4

Clock output select bits(1)

b6 b5 b4

0 0 0 : f2

0 0 1 : fC

0 1 0 : f4

0 1 1 : 1Hz

1 0 0 : f8

Other than above : Do not set.

Timer RE Real-Time Clock Precision Adjust Register(1)

Symbol

Address

After Reset

TREOPR

011Fh

00h

Bit Symbol

Bit Name

Function

Setting

Range

8-bit counter subtract bit(2)

8-bit counter add bit(2)

NOTES:

When this bit is set to 1, the correction value set

by D0 to D5 is subtracted from the 8-bit counter

value.

When read, the content is 0.

Use the MOV instruction for setting the TREOPR register.

Allow a period (s) of the XCIN clock × 2064 or more betw een w rites to the TREOPR register.

PLUS

MINUS

The correction value of the 8-bit

counter is stored.

When read, the content is 000000b.

00h to 3Ch

b7 b6 b5 b4

When this bit is set to 1, the correction value set

by D0 to D5 is added to the 8-bit counter value.

When read, the content is 0.

8-bit counter adjust bit

Write 1 to either the MINUS bit or the PLUS bit only once during each interrupt routine for the

w eek/day/hour/minute/second cycle.

When 00b or 11b is w ritten to bits MINUS and PLUS, the 8-bit counter value is not added or subtracted.

b3 b2

b1 b0

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