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R8C/2G 数据表(PDF) 224 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 224 Page - Renesas Technology Corp |
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224 / 344 page ![]() R8C/2G Group 17. Timers Rev.1.00 Apr 04, 2008 Page 204 of 318 REJ09B0387-0100 Figure 17.50 TRFCR1 Register Figure 17.51 TRFOUT Register Timer RF Control Register 1 Symbol Address After Reset TRFCR1 029Bh 00h Bit Symbol Bit Name Function RW NOTES: 1. 2. 3. 4. When the TMOD bit is set to 0 (input capture mode), set bits CCLR, and TRFC14 to TRFC17 to 0. When the TSTART bit in the TRFCR0 register is set to 0 (count stops), rew rite bits CCLR and TMOD. RW TRFC17 TRFC16 Compare 1 output select bits(2) b7 b6 CMP output w hen compare 0 is matched 0 0 : Unchanged 0 1 : Inverted 1 0 : “L” 1 1 : “H” If filter enabled, w hen the same value from the TRFI pin is sampled three times continuously, the input is determined. b3 b2 0 : Free-running operation 1 : Set TRF register to 0000h w hen compare 1 is matched. b1 b0 TIPF1 b7 b6 b5 b4 RW TRFC15 TIPF0 TMOD Timer RF operation mode select bit(3) CCLR TRFC14 TRFI filter select bits(1) When the TMOD bit is set to 0 (input capture mode), set bits ILVL2 to ILVL0 in the CMP1IC register to 000b (level 0) and set the IR bit to 0 (no interrupt requested). RW TRF register count operation select bit(2, 3) Compare 0 output select bits(2) b5 b4 CMP output w hen compare 0 is matched 0 0 : Unchanged 0 1 : Inverted 1 0 : “L” 1 1 : “H” RW b1 b0 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling 0 : Input capture mode(2, 4) 1 : Output compare mode RW RW Timer RF Output Control Register Symbol Address After Reset TRFOUT 02FFh 00h Bit Symbol Bit Name Function RW TRFOUT3 TRFO10 output enable bit RW RW RW TRFO00 to TRFO02 output invert bit RW 0 : Output disabled 1 : Output enabled 0 : Output not inverted 1 : Output inverted RW TRFOUT2 RW RW TRFO02 output enable bit TRFO00 output enable bit TRFO01 output enable bit b7 b6 b5 b4 b3 b2 b1 b0 TRFOUT1 TRFOUT0 TRFOUT7 TRFOUT6 RW TRFO12 output enable bit TRFOUT5 TRFO11 output enable bit TRFO10 to TRFO12 output invert bit TRFOUT4 |
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