R8CSLASH2G datasheet(227/344 Pages) RENESAS

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R8C/2G Group

17. Timers

Rev.1.00

Apr 04, 2008

Page 207 of 318

REJ09B0387-0100

17.4.1.1

Digital Filter

The TRFI input is sampled, and when the sampled input level matches three times, its level is determined.

Select the digital filter function and sampling clock by the TRFCR1 register.

Figure 17.53

Block Diagram of Digital Filter

Latch

Match

detection

circuit

Edge

detection

circuit

Sampling clock

TMOD

TRFC04 to TRFC03

TIPF1 to TIPF0

TRFI input

signal

Clock period selected by

bits TIPF1 to TIPF0

Sampling clock

TRFI input signal

Input signal

through digital

filtering

Transmission cannot be performed

without three times match because the

input signal is assumed to be noise.

Signal transmission delayed

up to five sampling clock

Recognition of the

signal change with

three times match

f32

TRFC03 to TRFC04: Bits in TRFCR0 register

TIPF0 to TIPF1 and TMOD: Bits in TRFCR1 register

Latch

Count source

= 01b

= 10b

= 11b

= 01b, 10b, 11b

= 00b

TIPF1 to TIPF0

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