R8CSLASH2G datasheet(231/344 Pages) RENESAS

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R8C/2G Group

17. Timers

Rev.1.00

Apr 04, 2008

Page 211 of 318

REJ09B0387-0100

Figure 17.55

Operating Example in Output Compare Mode (“L” and “H” Held Output in Count

Stops)

In output compare mode, the same PWM waveform is output from all of pins TRFO00 to TRFO02 and

TRFO10 to TRFO12 during count operation. Note that the output waveform can be inverted for pins TRFO00

to TRFO02 or for pins TRFO10 to TRFO12. The output can also be fixed at “L” or “H” for individual pins for

a given period.

The behavior when count operation stops can be selected from the following two options: the output level

before the count stops is maintained, or output is fixed at “L” or “H”.

The values in the compare i register can be read by reading the TRFMi (i = 0 or 1) register. Writing to the

TRFMi register causes the values to be stored in the compare i register in the following timing:

• If the TSTART bit is set to 0 (count stops)

Values are stored simultaneously with the write to the TRFMi register.

• If the TSTART bit is set to 1 (count starts) and the CCLR bit in the TRFCR1 register is set to 0 (free running)

Values are stored when the TRF register (counter) overflows.

• If the TSTART bit is set to 1 and the CCLR bit is set to 1 (TRF register set to 0000h at compare 1 match)

Values are stored when the compare 1 and TRF register (counter) values match.

Set to 0 by a program

TRFO00 output

Set to 1 by a program

P1_0 bit in

P1 register

TRFO10 output

P3_3 bit in

P3 register

TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)

TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)

TRFOUT6 bit in TRFOUT register = 0 (TRFO00 to TRFO02 output not inverted)

TRFOUT7 bit in TRFOUT register = 1 (TRFO10 to TRFO12 output inverted)

TSTART bit in TRFCR0 register = 1 (count starts)

The above applies under the following conditions.

CMP output

(internal signal)

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