R8CSLASH2G datasheet(235/344 Pages) RENESAS

235 / 344 page

R8C/2G Group

18. Serial Interface

Rev.1.00

Apr 04, 2008

Page 215 of 318

REJ09B0387-0100

Figure 18.3

Registers U0MR, U2MR and U0BRG, U2BRG

UARTi Transmit/Receive Mode Register (i = 0 or 2)

Symbol

Address

After Reset

U0MR

00A0h

00h

U2MR

0160h

00h

Bit Symbol

Bit Name

Function

b3 b2 b1 b0

SMD0

b7 b6 b5 b4

Serial I/O mode select bits

b2 b1 b0

0 0 0 : Serial interface disabled

0 0 1 : Clock synchronous serial I/O mode

1 0 0 : UART mode transfer data 7 bits long

1 0 1 : UART mode transfer data 8 bits long

1 1 0 : UART mode transfer data 9 bits long

Other than above : Do not set.

SMD1

SMD2

STPS

0 : 1 stop bit

1 : 2 stop bits

CKDIR

Odd/even parity select bit

Enable w hen PRYE = 1

0 : Odd parity

1 : Even parity

PRYE

Parity enable bit

0 : Parity disabled

1 : Parity enabled

Set to 0.

PRY

Internal/external clock select bit 0 : Internal clock

1 : External clock

Stop bit length select bit

—

(b7)

Reserved bit

UARTi Bit Rate Register (i = 0 or 2)(1, 2, 3)

Symbol

Address

After Reset

U0BRG

00A1h

Undefined

U2BRG

0161h

Undefined

Setting Range

NOTES:

00h to FFh

Function

Assuming the set value is n, UiBRG divides the count source by n+1

After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.

Use the MOV instruction to w rite to this register.

Write to this register w hile the serial I/O is neither transmitting nor receiving.

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