R8CSLASH2G datasheet(237/344 Pages) RENESAS

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R8C/2G Group

18. Serial Interface

Rev.1.00

Apr 04, 2008

Page 217 of 318

REJ09B0387-0100

Figure 18.5

Registers U0C1, U2C1 and U0RB, U2RB

UARTi Transmit/Receive Control Register 1 (i = 0 or 2)

Symbol

Address

After Reset

U0C1

00A5h

00000010b

U2C1

0165h

00000010b

Bit Symbol

Bit Name

Function

NOTES:

2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.

UARTi transmit interrupt cause

select bit

0 : Transmission buffer empty (TI=1)

1 : Transmission completed (TXEPT=1)

UiRRM

UARTi continuous receive mode

enable bit(2)

0 : Disables continuous receive mode

1 : Enables continuous receive mode

The RI bit is set to 0 w hen the higher byte of the UiRB register is read out.

—

(b7)

Receive complete flag(1)

0 : No data in UiRB register

1 : Data in UiRB register

0 : Data in UiTB register

1 : No data in UiTB register

—

Receive enable bit

b7 b6 b5 b4

b3 b2 b1 b0

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Transmit enable bit

0 : Disables transmission

1 : Enables transmission

Transmit buffer empty flag

0 : Disables reception

1 : Enables reception

UiIRS

—

(b6)

Reserved bit

Set to 0.

UARTi Receive Buffer Register (i = 0 or 2)(1)

Symbol

After Reset

U0RB

Undefined

U2RB

Undefined

NOTES:

—

(b7-b0)

—

Function

Receive data (D7 to D0)

Receive data (D8)

—

(b8)

—

(b15)

(b8)

Bit Symbol

Bit Name

Address

00A7h-00A6h

0167h-0166h

OER

Overrun error flag(2)

0 : No overrun error

1 : Overrun error

0 : No parity error

1 : Parity error

FER

Framing error flag(2)

0 : No framing error

1 : Framing error

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

—

(b11-b9)

Read out the UiRB register in 16-bit units.

Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b

(serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no

error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte

of the UiRB register is read out.

Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.

SUM

Error sum flag(2)

0 : No error

1 : Error

PER

Parity error flag(2)

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