R8CSLASH2G datasheet(239/344 Pages) RENESAS

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R8C/2G Group

18. Serial Interface

Rev.1.00

Apr 04, 2008

Page 219 of 318

REJ09B0387-0100

i = 0 or 2

NOTE:

1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous

serial I/O mode.

Table 18.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXDi pin outputs “H” level

between the operating mode selection of UARTi (i = 0 or 2) and transfer start. (If the NCH bit is set to 1 (N-channel

open-drain output), this pin is in a high-impedance state.)

Table 18.2

Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)

Bit

Function

UiTB

0 to 7

Set data transmission

UiRB

0 to 7

Data reception can be read

OER

Overrun error flag

UiBRG

0 to 7

Set bit rate

UiMR

SMD2 to SMD0

Set to 001b

CKDIR

Select the internal clock or external clock

UiC0

CLK1 to CLK0

Select the count source in the UiBRG register

TXEPT

Transmit register empty flag

NCH

Select TXDi pin output mode

CKPOL

Select the transfer clock polarity

UFORM

Select the LSB first or MSB first

UiC1

Set this bit to 1 to enable transmission/reception

Transmit buffer empty flag

Set this bit to 1 to enable reception

Reception complete flag

UiIRS

Select the UARTi transmit interrupt source

UiRRM

Set this bit to 1 to use continuous receive mode

Table 18.3

I/O Pin Functions in Clock Synchronous Serial I/O Mode

Pin Name

Function

Selection Method

TXD0 (P1_4)

Output serial data

(Outputs dummy data when performing reception only)

RXD0 (P1_5)

Input serial data

PD1_5 bit in PD1 register = 0

(P1_5 can be used as an input port when performing

transmission only)

CLK0 (P1_6)

Output transfer clock

CKDIR bit in U0MR register = 0

Input transfer clock

CKDIR bit in U0MR register = 1

PD1_6 bit in PD1 register = 0

TXD2 (P6_3)

Output serial data

(Outputs dummy data when performing reception only)

RXD2 (P6_4)

Input serial data

PD6_4 bit in PD6 register = 0

(P6_4 can be used as an input port when performing

transmission only)

CLK2 (P6_5)

Output transfer clock

CKDIR bit in U2MR register = 0

Input transfer clock

CKDIR bit in U2MR register = 1

PD6_5 bit in PD6 register = 0

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