R8CSLASH2G datasheet(230/344 Pages) RENESAS

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R8C/2G Group

17. Timers

Rev.1.00

Apr 04, 2008

Page 210 of 318

REJ09B0387-0100

Figure 17.54

Operating Example in Output Compare Mode

Value set in

TRFM1 register

0000h

Count starts

Match

Time

TSTART bit in

TRFCR0 register

IR bit in

CMP0IC register

Set to 1 by a program

IR bit in

CMP1IC register

Value set in

TRFM0 register

Match

TRFO00 output

TRFO10 output

Set to 0 when interrupt request is acknowledged,

or set by a program.

Set to 0 when interrupt request is

acknowledged, or set by a program.

When the count

stops, the value

is set to 0000h.

TRFC05 bit in TRFCR0 register = 1, TRFC06 bit in TRFCR0 register = 0 (“L” output when count stops)

CCLR bit in TRFCR1 register = 1 (TRF register is set to 0000h at compare 1 match occurrence)

TMOD bit in TRFCR1 register = 1 (output compare mode)

Bits TRFC15 to TRFC14 in TRFCR1 register = 11b (CMP output level is set to “H” at compare 0 match)

Bits TRFC17 to TRFC16 in TRFCR1 register = 10b (CMP output level is set to “L” at compare 1 match)

TRFOUT6 bit in TRFOUT register = 0 (not inverted)

TRFOUT7 bit in TRFOUT register = 1 (inverted)

TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)

TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)

P1_0 bit in P1 register = 1 (“H”)

P3_3 bit in P3 register = 1 (“H”)

The above applies under the following conditions.

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