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R8C/2G Group

17. Timers

Rev.1.00

Apr 04, 2008

Page 208 of 318

REJ09B0387-0100

17.4.2

Output Compare Mode

In output compare mode, when the value of the TRF register matches the value of the TRFM0 (compare 0

match) or TRFM1 (compare 1 match) register, a user-set level is output mode from the output-compare output

pin.

Table 17.15 shows the Output Compare Mode Specifications. Table 17.16 shows the Output in Output

Compare Mode (Example of TRFO00 Pin). Figure 17.54 shows an Operating Example in Output Compare

Mode. Figure 17.55 shows an Operating Example in Output Compare Mode (“L” and “H” Held Output in

Count Stops).

Table 17.15

Output Compare Mode Specifications

Item

Specification

Count sources

f1, f8, f32

Count operations

Increment

PWM waveform

PWM period: 1/fk × (n + 1)

“L” level width: 1/fk × (m + 1)

“H” level width: 1/fk × (n - m)

fk: Frequency of count source

m: Value set in the TRFM0 register

n: Value set in the TRFM1 register

Count start condition

The TSTART bit in the TRFCR0 register is set to 1 (count starts).

Count stop condition

The TSTART bit in the TRFCR0 register is set to 0 (count stops).

Interrupt request generation

timing

• When compare 0 match is generated [compare 0 interrupt]

• When compare 1 match is generated [compare 1 interrupt]

• When time RF overflows [timer RF interrupt].

TRFO00 to TRFO12 pin

functions

Programmable I/O port or output-compare output

Counter value reset timing

In the following cases, the value in the TRF register is set to 0000h.

• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).

• The CCLR bit in the TRFCR1 register is set to 1 (the TRF register is set to 0000h at

compare 1 match) in the compare 1 matches.

Read from timer

• The count value can be read out by reading the TRF register.

• The value in the compare register can be read out by reading registers TRFM0 and

TRFM1.

Write to timer

Write to the TRF register is disabled

Select functions

• Output-compare output pin selected

Either 1 pin or multiple pins among TRFO00 to TRFO02, or TRFO10 to TRFO12

(bits TRFOUT0 to TRFOUT5 in the TRFOUT register).

• Output level at the compare match

Selects “H”, “L”, inverted, or unchanged (bits TRFC14 to TRFC17 in the TRFCR1

• Output level inverted

Selects output level inverted or not inverted (bits TRFOUT6 to TRFOUT7 in the

TRFOUT register).

• Output level at the count stops

Selects “H”, “L”, or unchanged (bits TRFC05 to TRFC06 in the TRFCR0 register).

• Timing to set the TRF register to 0000h

Overflow or compare 1 match in the TRFM1 register (the CCLR bit in the TRFCR1

• TRFO11 pin select function

P3_4 or P3_7 is selected by the TRFOSEL bit in the PINSR4 register.

It applies under the following conditions.

• CMP output “H” when compare 0 is matched

• CMP output “L” when compare 1 is matched

• CMP output not inverted

n + 1

n - m

m + 1

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