R8CSLASH2G datasheet(259/344 Pages) RENESAS

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R8C/2G Group

19. Hardware LIN

Rev.1.00

Apr 04, 2008

Page 239 of 318

REJ09B0387-0100

Figure 19.10

Example of Header Field Reception Flowchart (3)

Hardware LIN Read the Synch Field measurement-

completed flag

SFDCT flag in the LINST register

UART0 Set the UART0 communication rate

U0BRG register

Communication via UART0

(The SBDCT flag is set when the

timer RA counter underflows upon

reaching the terminal count.)

SFDCT = 1 ?

YES

UART0 Communication via UART0

Clock asynchronous serial interface (UART) mode

Transmit ID field

Hardware LIN measures the Synch

Field.

The interrupt of timer RA may be

used (the SBDCT flag is set when

the timer RA counter underflows

upon reaching the terminal count).

When the SBE bit in the LINCR

Synch Field measurement is

completed), timer RA may be used

in timer mode after the SFDCT bit

in the LINST register is set to 1.

Set a communication rate based on

the Synch Field measurement

result.

YES

Timer RA Set the Synch Break width again

TRAPRE register

TRA register

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