R8CSLASH2G datasheet(257/344 Pages) RENESAS

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R8C/2G Group

19. Hardware LIN

Rev.1.00

Apr 04, 2008

Page 237 of 318

REJ09B0387-0100

Figure 19.8

Example of Header Field Reception Flowchart (1)

Set the count source and registers

TRA and TRAPRE as appropriate

for the Synch Break period.

Select the timing at which to

unmask the RXD0 input for UART0.

If the RXD0 input is chosen to be

unmasked after detection of Synch

Break, the Synch Field signal is

also input to UART0.

For the hardware LIN

function, set the TIOSEL bit

in the TRAIOC register to 1.

Timer RA Set to pulse width measurement mode

Bits TMOD0 to TMOD2 in the TRAMR register

← 011b

Timer RA Set the pulse width measurement level low

TEDGSEL bit in the TRAIOC register

← 0

Timer RA Set the INT1/TRAIO pin to P1_5

TIOSEL bit in the TRAIOC register

← 1

Timer RA Set the count source (f1, f2, f8, fOCO)

Bits TCK0 to TCK2 in the TRAMR register

Timer RA Set the Synch Break width

TRAPRE register

TRA register

Hardware LIN Set the LIN operation to stop

LINE bit in the LINCR register

← 0

Hardware LIN Set to slave mode

MST bit in the LINCR register

← 0

Hardware LIN Set the RXD0 input unmasking timing

(After Synch Break detection, or after Synch

Field measurement)

SBE bit in the LINCR register

Hardware LIN Set the register to enable interrupts

(Bus collision detection, Synch Break detection,

Synch Field measurement)

Bits BCIE, SBIE, SFIE in the LINCR register

Hardware LIN Set the LIN operation to start

LINE bit in the LINCR register

← 1

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