R8CSLASH2G datasheet(253/344 Pages) RENESAS

253 / 344 page

R8C/2G Group

19. Hardware LIN

Rev.1.00

Apr 04, 2008

Page 233 of 318

REJ09B0387-0100

19.4

Functional Description

19.4.1

Master Mode

Figure 19.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.

Figures 19.5 and 19.6 show an Example of Header Field Transmission Flowchart.

When transmitting a header field, the hardware LIN operates as described below.

(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware

LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for

timer RA.

(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of

the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the

LINCR register is set to 1, it generates a timer RA interrupt.

(3) The hardware LIN transmits 55h via UART0.

(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.

(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.

Figure 19.4

Typical Operation when Sending a Header Field

TXD0 pin

Synch Break

SBDCT flag in the

LINST register

IR bit in the TRAIC

Synch Field

IDENTIFIER

(1)

(2)

(3)

(4)

(5)

Set by writing 1 to the

B1CLR bit in the LINST

Cleared to 0 upon

acceptance of interrupt

request or by a program

Shown above is the case where

LINE = 1, MST = 1, SBIE = 1

R8C/2G 数据表(PDF) 253 Page - Renesas Technology Corp

R8C/2G 数据表(HTML) 253 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载