R8CSLASH2G datasheet(251/344 Pages) RENESAS

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R8C/2G Group

19. Hardware LIN

Rev.1.00

Apr 04, 2008

Page 231 of 318

REJ09B0387-0100

19.3

The hardware LIN contains the registers listed below.

These registers are detailed in Figures 19.2 and 19.3.

• LIN Control Register (LINCR)

• LIN Status Register (LINST)

Figure 19.2

LINCR Register

LIN Control Register

Symbol

Address

After Reset

LINCR

0106h

00h

Bit Symbol

Bit Name

Function

NOTES:

LIN operation start bit

0 : Causes LIN to stop

1 : Causes LIN to start operating(3)

LIN operation mode setting bit(2) 0 : Slave mode

(Synch Break detection circuit actuated)

1 : Master mode

(timer RA output OR’ed w ith TXD0)

0 : Disables Synch Field measurement-

completed interrupt

1 : Enables Synch Field measurement-

completed interrupt

SFIE

Synch Field measurement-

completed interrupt enable bit

b7 b6 b5 b4 b3 b2 b1 b0

0 : RXD0 input enabled

1 : RXD0 input disabled

When this bit is set to 1, timer RA input is

enabled and RXD0 input is disabled.

When read, the content is 0.

RXD0 input status flag

Synch Break detection start bit(1)

Synch Break detection interrupt

enable bit

Bus collision detection interrupt

enable bit

0 : Disables Synch Break detection interrupt

1 : Enables Synch Break detection interrupt

0 : Disables bus collision detection interrupt

1 : Enables bus collision detection interrupt

SBIE

BCIE

RXDSF

LSTART

Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 19.5 Exam ple of

Header Field Transm ission Flow chart (1) and Figure 19.9 Exam ple of Header Field Reception Flow chart

(2).)

Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).

SBE

After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.

0 : Unmasked after Synch Break is detected

1 : Unmasked after Synch Field measurement

is completed

RXD0 input unmasking timing

select bit (effective only in slave

mode)

MST

LINE

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