R8CSLASH2G datasheet(247/344 Pages) RENESAS

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R8C/2G Group

18. Serial Interface

Rev.1.00

Apr 04, 2008

Page 227 of 318

REJ09B0387-0100

18.2.1

Bit Rate

In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 2) register.

Figure 18.11

Calculation Formula of UiBRG (i = 0 or 2) Register Setting Value

Table 18.7

Bit Rate Setting Example in UART Mode (Internal Clock Selected)

Bit Rate (bps)

BRG Count Source

System Clock = 8 MHz

UiBRG Setting Value

Actual Time (bps)

Error (%)

1200

51 (33h)

1201.92

0.16

2400

25 (19h)

2403.85

0.16

4800

12 (0Ch)

4807.69

0.16

9600

51 (33h)

9615.38

0.16

14400

34 (22h)

14285.71

-0.79

19200

25 (19h)

19230.77

0.16

28800

16 (10h)

29411.76

2.12

31250

15 (0Fh)

31250.00

0.00

38400

12 (0Ch)

38461.54

0.16

51200

9 (09h)

50000.00

-2.34

UART mode

• Internal clock selected

UiBRG register setting value =

Bit Rate

× 16

- 1

Fj: Count source frequency of the UiBRG register (f1, f8, or f32)

• External clock selected

fEXT

Bit Rate

× 16

- 1

fEXT: Count source frequency of the UiBRG register (external clock)

UiBRG register setting value =

i = 0 or 2

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