R8CSLASH2G datasheet(244/344 Pages) RENESAS

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R8C/2G Group

18. Serial Interface

Rev.1.00

Apr 04, 2008

Page 224 of 318

REJ09B0387-0100

i = 0 or 2

NOTES:

1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long; bits 0 to 7

when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.

2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits

long.

Table 18.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 2) operating mode is selected, the

TXDi pin outputs “H” level. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-

impedance state) until transfer starts.)

Table 18.5

Registers Used and Settings for UART Mode

Bit

Function

UiTB

0 to 8

Set transmit data(1)

UiRB

0 to 8

Receive data can be read(1, 2)

OER,FER,PER,SUM

Error flag

UiBRG

0 to 7

Set a bit rate

UiMR

SMD2 to SMD0

Set to 100b when transfer data is 7 bits long

Set to 101b when transfer data is 8 bits long

Set to 110b when transfer data is 9 bits long

CKDIR

Select the internal clock or external clock

STPS

Select the stop bit

PRY, PRYE

Select whether parity is included and whether odd or even

UiC0

CLK0, CLK1

Select the count source for the UiBRG register

TXEPT

Transmit register empty flag

NCH

Select TXDi pin output mode

CKPOL

Set to 0

UFORM

LSB first or MSB first can be selected when transfer data is 8 bits long.

Set to 0 when transfer data is 7 or 9 bits long.

UiC1

Set to 1 to enable transmit

Transmit buffer empty flag

Set to 1 to enable receive

Receive complete flag

UiIRS

Select the source of UARTi transmit interrupt

UiRRM

Set to 0

Table 18.6

I/O Pin Functions in UART Mode

Pin name

Function

Selection Method

TXD0 (P1_4) Output serial data

(Cannot be used as a port when performing reception only)

RXD0 (P1_5) Input serial data

PD1_5 bit in PD1 register = 0

(P1_5 can be used as an input port when performing

transmission only)

CLK0 (P1_6) Programmable I/O Port CKDIR bit in U0MR register = 0

Input transfer clock

CKDIR bit in U0MR register = 1

PD1_6 bit in PD1 register = 0

TXD2 (P6_3) Output serial data

(Cannot be used as a port when performing reception only)

RXD2 (P6_4) Input serial data

PD6_4 bit in PD6 register = 0

(P6_4 can be used as an input port when performing

transmission only)

CLK2 (P6_5) Programmable I/O Port CKDIR bit in U2MR register = 0

Input transfer clock

CKDIR bit in U2MR register = 1

PD6_5 bit in PD6 register = 0

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