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R8C/2G 数据表(PDF) 249 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 249 Page - Renesas Technology Corp |
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249 / 344 page  R8C/2G Group 19. Hardware LIN Rev.1.00 Apr 04, 2008 Page 229 of 318 REJ09B0387-0100 19. Hardware LIN The hardware LIN performs LIN communication in cooperation with timer RA and UART0. 19.1 Features The hardware LIN has the features listed below. Figure 19.1 shows a Block Diagram of Hardware LIN. Master mode • Generates Synch Break • Detects bus collision Slave mode • Detects Synch Break • Measures Synch Field • Controls Synch Break and Synch Field signal inputs to UART0 • Detects bus collision NOTE: 1. The WakeUp function is detected by INT1. Figure 19.1 Block Diagram of Hardware LIN Timer RA UART0 Interrupt control circuit Bus collision detection circuit Synch Field control circuit RXD0 input control circuit RXD0 pin TXD0 pin LSTART bit SBE bit LINE bit Timer RA interrupt TIOSEL = 0 Hardware LIN TIOSEL = 1 RXD data Timer RA underflow signal BCIE, SBIE, and SFIE bits UART0 transfer clock UART0 TE bit Timer RA output pulse UART0 TXD data MST bit LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register TIOSEL: Bit in TRAIOC register TE: Bit in U0C1 register |
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