R8CSLASH2G datasheet(254/344 Pages) RENESAS

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R8C/2G Group

19. Hardware LIN

Rev.1.00

Apr 04, 2008

Page 234 of 318

REJ09B0387-0100

Figure 19.5

Example of Header Field Transmission Flowchart (1)

Timer RA Set to timer mode

Bits TMOD0 to TMOD2 in TRAMR register

← 000b

Timer RA Set the pulse output level from low to start

TEDGSEL bit in TRAIOC register

← 1

Timer RA Set the INT1/TRAIO pin to P1_5

TIOSEL bit in TRAIOC register

← 1

Timer RA Set the count source (f1, f2, f8, fOCO)

Bits TCK0 to TCK2 in TRAMR register

Timer RA Set the Synch Break width

TRAPRE register

TRA register

Hardware LIN Set to master mode

MST bit in LINCR register

← 1

Hardware LIN Set the LIN operation to start

LINE bit in LINCR register

← 1

Hardware LIN Set the register to enable interrupts

(Bus collision detection, Synch Break detection,

Synch Field measurement)

Bits BCIE, SBIE, SFIE in LINCR register

Hardware LIN Clear the status flags

(Bus collision detection, Synch Break detection,

Synch Field measurement)

Bits B2CLR, B1CLR, B0CLR in LINST register

← 1

Set the count source and

registers TRA and TRAPRE

as suitable for the Synch

Break period.

During master mode, the

Synch Field measurement-

completed interrupt cannot be

used.

For the hardware LIN

function, set the TIOSEL bit

in the TRAIOC register to 1.

UART0

Set to transmit/receive mode

(Transfer data length: 8 bits, Internal clock, 1 stop bit,

Parity disabled)

U0MR register

UART0

Set the BRG count source (f1, f8, f32)

Bits CLK0 to CLK2 in U0C0 register

UART0

Set the bit rate

U0BRG register

Hardware LIN Set the LIN operation to stop

LINCR register LINE bit

← 0

Set the BRG count source

and U0BRG register as

appropriate for the bit rate.

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