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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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R8C/2G 数据表(PDF) 264 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 264 Page - Renesas Technology Corp |
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264 / 344 page  R8C/2G Group 20. Flash Memory Rev.1.00 Apr 04, 2008 Page 244 of 318 REJ09B0387-0100 20. Flash Memory 20.1 Overview Rewrite operations to the flash memory can be performed in three modes : CPU rewrite, standard serial I/O, and parallel I/O. Table 20.1 lists the Flash Memory Performance (refer to Table 1.1 Specifications for R8C/2G Group for items not listed in Table 20.1). NOTE: 1. Definition of programming and erasure endurance. The programming and erasure endurance is defined on a per-block basis. Table 20.1 Flash Memory Performance Item Specification Flash memory operating mode 3 modes (CPU rewrite, standard serial I/O, and parallel I/O) Division of erase block Refer to Figure 20.1 Programming method Byte unit Erase method Block erase Programming and erasure control method Program and erase control by software command Protection method Program ROM protection by FMR0 register Number of commands 5 commands Programming and erasure endurance(1) Blocks 0 and 1 (program ROM) 100 times Programming and erasure voltage VCC = 2.7 to 5.5 V ID code check function Standard serial I/O mode supported ROM code protect Parallel I/O mode supported Table 20.2 Flash Memory Rewrite Modes Flash Memory Rewrite Mode CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Function User ROM area is rewritten by executing software commands from the CPU. User ROM area is rewritten by a dedicated serial programmer. User ROM area is rewritten by a dedicated parallel programmer. Areas which can be rewritten User ROM area User ROM area User ROM area Rewrite Program User program Standard boot program – |
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