R8CSLASH2G datasheet(267/344 Pages) RENESAS

267 / 344 page

R8C/2G Group

20. Flash Memory

Rev.1.00

Apr 04, 2008

Page 247 of 318

REJ09B0387-0100

20.3.2

ROM Code Protect Function

The ROM protect function prevents the contents of the flash memory from being read, rewritten, or erased by

means of the OFS register when parallel I/O mode is used.

Figure 20.2 shows the OFS Register. Refer to 15. Option Function Select Area for details of the OFS register.

The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables

reading or changing the contents of the on-chip flash memory.

Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O

mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or

standard serial I/O mode.

Figure 20.2

OFS Register

Option Function Select Register(1)

Symbol

Address

When Shipping

OFS

0FFFFh

FFh(3)

Bit Symbol

Bit Name

Function

NOTES:

3. If the block including the OFS register is erased, FFh is set to the OFS register.

—

(b6)

Reserved bit

Set to 1.

CSPROINI

Count source protect

mode after reset select

bit

0 : Count source protect mode enabled after reset

1 : Count source protect mode disabled after reset

Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0

(voltage monitor 0 reset enabled after hardw are reset).

ROMCP1

ROM code protect bit

0 : ROM code protect enabled

1 : ROM code protect disabled

ROMCR

ROM code protect

disabled bit

0 : ROM code protect disabled

1 : ROMCP1 enabled

—

(b1)

Reserved bit

Set to 1.

WDTON

Watchdog timer start

select bit

0 : Starts w atchdog timer automatically after reset

1 : Watchdog timer is inactive after reset

b7 b6 b5 b4 b3 b2 b1 b0

—

(b4)

Reserved bit

Set to 1.

The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not

w rite additions to the OFS register.

LVD0ON

Voltage detection 0

circuit start bit(2)

0 : Voltage monitor 0 reset enabled after hardw are

reset

1 : Voltage monitor 0 reset disabled after hardw are

reset

R8C/2G 数据表(PDF) 267 Page - Renesas Technology Corp

R8C/2G 数据表(HTML) 267 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

R8C/2G 数据表(PDF) 267 Page - Renesas Technology Corp

R8C/2G 数据表(HTML) 267 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载