R8CSLASH2G datasheet(289/344 Pages) RENESAS

289 / 344 page

R8C/2G Group

20. Flash Memory

Rev.1.00

Apr 04, 2008

Page 269 of 318

REJ09B0387-0100

20.7

Notes on Flash Memory

20.7.1

CPU Rewrite Mode

20.7.1.1

Operating Speed

Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit

in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.

20.7.1.2

Prohibited Instructions

The following instructions cannot be used in EW0 mode because they reference data in the flash memory:

UND, INTO, and BRK.

20.7.1.3

Non-Maskable Interrupts

• EW0 Mode

Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comparator 2 interrupt

request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash

memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts.

As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal

value may not be readable. Execute auto-erasure again and ensure it completes normally.

The watchdog timer does not stop during command operation, so that interrupt requests may be generated.

Initialize the watchdog timer regularly.

Do not use the address match interrupt while a command is being executed because the vector of the

address match interrupt is allocated in ROM.

Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is

allocated in block 0.

• EW1 Mode

Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comparator 2 interrupt

request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash

memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts.

As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal

value may not be readable. Execute auto-erasure again and ensure it completes normally.

The watchdog timer does not stop even during command operation, so that interrupt requests may be

generated. Initialize the watchdog timer by using the erase-suspend function.

Do not use the address match interrupt while a command is being executed because the vector of the

address match interrupt is allocated in ROM.

Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is

allocated in block 0.

R8C/2G 数据表(PDF) 289 Page - Renesas Technology Corp

R8C/2G 数据表(HTML) 289 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载