H8SSLASH2225 datasheet(216/1071 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 130 of 982

REJ09B0054-0500

• Interrupt priority register J (IPRJ)

• Interrupt priority register K (IPRK)

• Interrupt priority register L (IPRL)

• Interrupt priority register O (IPRO)

5.3.1

Interrupt Priority Registers A to L, and O (IPRA to IPRL, IPRO)

The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for

interrupt sources other than NMI. The correspondence between interrupt sources and IPR settings

is shown in table 5.2. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 0 to 2

and 4 to 6 sets the priority of the corresponding interrupt.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0, and cannot be modified.

IPR6

IPR5

IPR4

R/W

Sets the priority of the corresponding interrupt source

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)



Reserved

This bit is always read as 0, and cannot be modified.

IPR2

IPR1

IPR0

R/W

Sets the priority of the corresponding interrupt source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

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