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ST7263BEx 数据表(PDF) 157 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 157 Page - STMicroelectronics |
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157 / 186 page ![]() ST7263Bxx Electrical characteristics Doc ID 7516 Rev 8 157/186 Figure 73 and Figure 74 show the reset circuit which protects the device against parasitic resets: ● The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). ● Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section Table 72.: Asynchronous RESET pin. Otherwise the reset will not be taken into account internally. ● Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in Section Table 56.: Current characteristics. When the LVD is enabled: ● It is recommended not to connect a pull-up resistor or capacitor. A 10 nF pull-down capacitor is required to filter noise on the reset line. ● In case a capacitive power supply is used, it is recommended to connect a 1 M Ω pull- down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5 µA to the power consumption of the MCU). ● Tips when using the LVD: a) Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above). b) Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100 nF + 1 M Ω pull-down on the RESET pin. c) The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps a) and b) above are sufficient for a robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a 5 µF to 20 µF capacitor. Figure 73. RESET pin protection when LVD is enabled 0.01 μF ST72XXX PULSE GENERATOR Filter RON VDD WATCHDOG LVD RESET INTERNAL RESET RESET EXTERNAL Required 1M Ω Optional |
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