ST7263BEx datasheet(162/186 Pages) STMICROELECTRONICS

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Electrical characteristics

ST7263Bxx

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Doc ID 7516 Rev 8

Table 77 gives the values to be written in the I2CCCR register to obtain the required I2C

SCL line frequency.

13.11

8-bit ADC

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Table 77.

SCL frequency(1)(2)(3)(4)

fSCL

(kHz)

I2CCCR Value

fCPU=4 MHz

fCPU=8 MHz

VDD = 4.1 V

VDD = 5 V

VDD = 4.1 V

VDD = 5 V

RP=3.3 kΩ RP=4.7 kΩ RP=3.3 kΩ RP=4.7 kΩ RP=3.3 kΩ RP=4.7 kΩ RP=3.3 kΩ RP=4.7 kΩ

400

83h

300

85h

200

83h

8Ah

89h

8Ah

100

10h

24h

23h

24h

23h

24h

4Ch

5Fh

FFh

Legend: RP = External pull-up resistance; fSCL = I

2C speed; NA = not achievable.

The above variations depend on the accuracy of the external components used.

For speeds around 200 kHz, achieved speed can have

±5% tolerance.

For other speed ranges, achieved speed can have

±2% tolerance.

Table 78.

8-bit ADC characteristics

Symbol

Parameter

Conditions

Min

Typ(1)

Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V.

Max

Unit

fADC

ADC clock frequency

MHz

VAIN

Conversion range voltage(2)

When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS.

VSSA

-VDDA

RAIN

External input resistor

10(3)

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than

10k

Ω). Data based on characterization results, not tested in production.

κΩ

CADC

Internal sample and hold

capacitor

-6

tSTAB

Stabilization time after ADC

enable

fCPU=8 MHz,

fADC=2 MHz

0(4)

The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable

is then always valid.

µs

tADC

Conversion time (Sample+Hold)

- Sample capacitor loading time

- Hold conversion time

1/fADC

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