HCS12 datasheet(183/452 Pages) FREESCALE

183 / 452 page

Glossary

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

183

Operation:

(D)

÷ (X) ⇒ X; Remainder ⇒ D

Description:

Divides an unsigned 16-bit numerator in double accumulator D by an

unsigned 16-bit denominator in index register X, producing an unsigned

16-bit quotient in X and an unsigned 16-bit remainder in D. If both the

numerator and the denominator are assumed to have radix points in the

same positions, the radix point of the quotient is to the left of bit 15. The

numerator must be less than the denominator. In the case of overflow

(denominator is less than or equal to the numerator) or division by zero, the

quotient is set to $FFFF, and the remainder is indeterminate.

FDIV is equivalent to multiplying the numerator by 216 and then performing

32 by 16-bit integer division. The result is interpreted as a binary-weighted

fraction, which resulted from the division of a 16-bit integer by a larger 16-bit

integer. A result of $0001 corresponds to 0.000015, and $FFFF

corresponds to 0.9998. The remainder of an IDIV instruction can be

resolved into a binary-weighted fraction by an FDIV instruction. The

remainder of an FDIV instruction can be resolved into the next 16 bits of

binary-weighted fraction by another FDIV instruction.

FDIV

Fractional Divide

FDIV

CCR Details:

HIN

–––––

∆∆∆

Z: Set if quotient is $0000; cleared otherwise

V: 1 if X

≤ D

Set if the denominator was less than or equal to the numerator;

cleared otherwise

C: X15

• X14 • X13 • X12 •... • X3 • X2 • X1 • X0

Set if denominator was $0000; cleared otherwise

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

FDIV

INH

18 11

OffffffffffO

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