HCS12 datasheet(185/452 Pages) FREESCALE

185 / 452 page

Glossary

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

185

Operation:

(Counter) + 1

⇒ Counter

If (Counter) not = 0, then (PC) + $0003 + Rel

⇒ PC

Description:

Add one to the specified counter register A, B, D, X, Y, or SP. If the counter

destination. The IBNE instruction is encoded into three bytes of machine

code including a 9-bit relative offset (–256 to +255 locations from the start

of the next instruction).

DBNE and TBNE instructions are similar to IBNE except that the counter is

decremented or tested rather than being incremented. Bits 7 and 6 of the

instruction postbyte are used to determine which operation is to be

performed.

IBNE

Increment and Branch if Not Equal to Zero

IBNE

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code(1)

1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (IBEQ –

0) or not zero (IBNE – 1) versions, and bit 0 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should be 1:0 for IBNE.

Access Detail

HCS12

M68HC12

IBNE abdxys, rel9

REL

04 lb rr

PPP/PPO

PPP

Count

Bits 2:0

Source Form

Object Code

(If Offset is Positive)

Object Code

(If Offset is Negative)

000

001

IBNE A, rel9

IBNE B, rel9

04 A0 rr

04 A1 rr

04 B0 rr

04 B1 rr

100

101

110

111

IBNE D, rel9

IBNE X, rel9

IBNE Y, rel9

IBNE SP, rel9

04 A4 rr

04 A5 rr

04 A6 rr

04 A7 rr

04 B4 rr

04 B5 rr

04 B6 rr

04 B7 rr

HCS12 数据表(PDF) 185 Page - Freescale Semiconductor, Inc

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