910GL datasheet(200/426 Pages) INTEL

200 / 426 page

Device 2 Function 1 (D2:F1) Configuration Registers

(Intel® 82915G/82915GV/82915GL/ 82910GL Only)

200

Datasheet

10.1.15

MINGNT—Minimum Grant Register (D2:F1)

PCI Device:

Address Offset:

3Eh

Default Value:

00h

Access:

Size:

8 bits

This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It

is implemented as common hardware with two access addresses.

10.1.16

MAXLAT—Maximum Latency (D2:F1)

PCI Device:

Address Offset:

3Fh

Default Value:

00h

Access:

Size:

8 bits

This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It

is implemented as common hardware with two access addresses.

10.1.17

MCAPPTR—Mirror of Dev0 Capability Pointer (D2:F1)

(Mirrored_D0_34)

PCI Device:

Function:

Address Offset:

44h

Size:

8 bits

This register is a Read Only copy of Device 0, Offset 34h register.

10.1.18

MCAPID—Mirror of Dev0 Capability Identification (D2:F1)

(Mirrored_D0_E0)

PCI Device:

Function:

Address Offset:

48h

Size:

72 bits

This register is a Read-Only copy of Device 0, Offset E0h register.

10.1.19

MGGC—Mirror of Dev0 GMCH Graphics Control (D2:F1)

(Mirrored_D0_52)

PCI Device:

Address Offset:

52h

Size:

16 bits

This register is a Read Only copy of Device 0, Offset 52h register.

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