910GL datasheet(198/426 Pages) INTEL

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Device 2 Function 1 (D2:F1) Configuration Registers

(Intel® 82915G/82915GV/82915GL/ 82910GL Only)

198

Datasheet

10.1.8

MLT2—Master Latency Timer (D2:F1)

PCI Device:

Address Offset:

0Dh

Default Value:

00h

Access:

Size:

8 bits

This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It

is implemented as common hardware with two access addresses.

10.1.9

HDR2—Header Type Register (D2:F1)

PCI Device:

Address Offset:

0Eh

Default Value:

80h

Access:

Size:

8 bits

This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It

is implemented as common hardware with two access addresses.

10.1.10

MMADR—Memory Mapped Range Address (D2:F1)

PCI Device:

Address Offset:

10h

Default Value:

00000000h

Access:

RO, R/W

Size:

32 bits

This register requests allocation for the IGD registers and instruction ports. The allocation is for

512 KB and the base address is defined by bits [31:19].

Bit

Access &

Default

Description

31:19

R/W

0000h

Memory Base Address: Set by the OS, these bits correspond to address

signals [31:19].

18:4

0000h

Address Mask: Hardwired to 0s to indicate 512-KB address range.

Prefetchable Memory: Hardwired to 0 to prevent prefetching.

2:1

00b

Memory Type: Hardwired to 0s to indicate 32-bit address.

Memory / IO Space: Hardwired to 0 to indicate memory space.

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