910GL datasheet(197/426 Pages) INTEL

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Device 2 Function 1 (D2:F1) Configuration Registers

(Intel® 82915G/82915GV/82915GL/ 82910GL Only)

Datasheet

197

10.1.5

RID2—Revision Identification (D2:F1)

PCI Device:

Address Offset:

08h

Default Value:

See description below

Access:

Size:

8 bits

This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It

is implemented as common hardware with two access addresses.

10.1.6

CC—Class Code Register (D2:F1)

PCI Device:

Address Offset:

09h

Default Value:

038000h

Access:

Size:

24 bits

This register contains the device programming interface information related to the Sub-Class

Code and Base Class Code definition for the IGD. This register also contains the Base Class Code

and the function sub-class in relation to the Base Class Code.

Bit

Access &

Default

Description

23:16

03h

Base Class Code (BCC): This is an 8-bit value that indicates the base class

code for the GMCH.

03h = Display Controller.

15:8

80h

Sub-Class Code (SUBCC)

80h = Non VGA

7:0

00h

Programming Interface (PI)

00h = Hardwired as a Display controller.

10.1.7

CLS—Cache Line Size (D2:F1)

PCI Device:

Address Offset:

0Ch

Default Value:

00h

Access:

Size:

8 bits

This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It

is implemented as common hardware with two access addresses.

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910GL 数据表(PDF) 197 Page - Intel Corporation

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