910GL datasheet(194/426 Pages) INTEL

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Device 2 Function 1 (D2:F1) Configuration Registers

(Intel® 82915G/82915GV/82915GL/ 82910GL Only)

194

Datasheet

Address

Offset

Symbol

Default

Value

Access

48–50h

MCAPID

Mirror of Dev0 Capability Identification

51h

—

Reserved

—

52–53h

MGGC

Mirror of Dev0 GMCH Graphics Control

54–57h

MDEVENdev0f0

Mirror of Dev0 Device Enable

58–5Bh

—

Reserved

—

5C–5Fh

BSM

Base of Stolen Memory Register

07800000h

60–CFh

—

Reserved

0000h

—

D0–D1h

PMCAPID

Power Management Capabilities ID

0001h

D2–D3h

PMCAP

Power Management Capabilities

0022h

D4–D5h

PMCS

Power Management Control/Status

0000h

RO, R/W

D6–DFh

—

Reserved

—

E0–E1h

SWSMI

Software SMI

0000h

R/W

E2–FBh

—

Reserved

—

FC–FFh

ASLS

ASL Storage

00000000h

R/W

10.1

Device 2 Function 1 Configuration Register Details

(D2:F1)

10.1.1

VID2—Vendor Identification (D2:F1)

PCI Device:

Address Offset:

00h

Default Value:

8086h

Access:

Size:

16 bits

This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It

is implemented as common hardware with two access addresses.

10.1.2

DID2—Device Identification (D2:F1)

PCI Device:

Address Offset:

02h

Default Value:

2782h

Access:

Size:

16 bits

This register is unique in Device 2, Function 1 (the Device 2, Function 0 DID is separate). This

difference in Device ID is necessary for allowing distinct Plug and Play enumeration of function 1

when both function 0 and function 1 have the same class code.

910GL 数据表(PDF) 194 Page - Intel Corporation

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910GL 数据表(PDF) 194 Page - Intel Corporation

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