910GL datasheet(196/426 Pages) INTEL

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Device 2 Function 1 (D2:F1) Configuration Registers

(Intel® 82915G/82915GV/82915GL/ 82910GL Only)

196

Datasheet

10.1.4

PCISTS2—PCI Status (D2:F1)

PCI Device:

Address Offset:

06h

Default Value:

0090h

Access:

Size:

16 bits

PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and

PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the

IGD.

Bit

Access &

Default

Description

Detected Parity Error (DPE): Since the IGD does not detect parity; this bit is

always hardwired to 0.

Signaled System Error (SSE): The IGD never asserts SERR#; therefore, this

bit is hardwired to 0.

Received Master Abort Status (RMAS): The IGD never gets a Master Abort,

therefore this bit is hardwired to 0.

Received Target Abort Status (RTAS): The IGD never gets a Target Abort,

therefore this bit is hardwired to 0.

Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use

target abort semantics.

10:9

00b

DEVSEL Timing (DEVT): These bits are hardwired to 00.

Master Data Parity Error Detected (DPD): Since Parity Error Response is

hardwired to disabled (and the IGD does not do any parity detection), this bit is

hardwired to 0.

Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back

when the transactions are not to the same agent.

User Defined Format (UDF). Hardwired to 0.

66 MHz PCI Capable (66C). Hardwired to 0.

Capability List (CLIST): This bit is set to 1 to indicate that the register at 34h

provides an offset into the function’s PCI Configuration Space containing a

pointer to the location of the first item in the list.

Interrupt Status: Hardwired to 0.

2:0

Reserved

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