910GL datasheet(190/426 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0)

(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)

190

Datasheet

9.1.30

PMCS—Power Management Control/Status (D2:F0)

PCI Device:

Address Offset:

D4h

Default Value:

0000h

Access:

RO, R/W

Size:

16 bits

Bit

Access &

Default

Description

PME_Status: This bit is 0 to indicate that IGD does not support PME# generation

from D3 (cold).

14:9

Reserved

PME_En: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.

7:2

Reserved

1:0

R/W

00b

Power State: This field indicates the current power state of the IGD and can be

used to set the IGD into a new power state. If software attempts to write an

unsupported state to this field, the write operation must complete normally on the

bus, but the data is discarded and no state change occurs.

On a transition from D3 to D0 the graphics controller is optionally reset to initial

values. Behavior of the graphics controller in supported states is detailed in the

power management section.

00 = D0 (Default)

01 = D1 (Not Supported)

10 = D2 (Not Supported)

11 = D3

910GL 数据表(PDF) 190 Page - Intel Corporation

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