MPC8544E datasheet(107/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

107

System Design Information

Note the following:

•AVDD_SRDS should be a filtered version of SVDD.

•

Signals on the SerDes interface are fed from the XVDD power plane.

21.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8544E system, and the device

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD pin

of the device. These decoupling capacitors should receive their power from separate VDD, TVDD, BVDD,

OVDD, GVDD, and LVDD; and GND power planes in the PCB, utilizing short low impedance traces to

minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern.

Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD, TVDD, BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the

smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating

to ensure the quick response time necessary. They should also be connected to the power and ground

planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor

for best values and types and quantity of bulk capacitors.

21.4

SerDes Block Power Supply Decoupling Recommendations

The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low

jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is

outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections

from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

•

First, the board should have at least 10

× 10-nF SMT ceramic chip capacitors as close as possible

to the supply balls of the device. Where the board has blind vias, these capacitors should be placed

directly below the chip supply and ground connections. Where the board does not have blind vias,

these capacitors should be placed in a ring around the device as close to the supply and ground

connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be

done for all SerDes supplies.

•

Third, between the device and any SerDes voltage regulator there should be a 10-µF, low

equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT

tantalum chip capacitor. This should be done for all SerDes supplies.

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