MPC8544E datasheet(110/117 Pages) FREESCALE

110 / 117 page

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

110

Freescale Semiconductor

System Design Information

been encoded such that a high voltage level puts the device into the default state and external resistors are

needed only when non-default settings are required by the user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value

of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus

configured.

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up

devices.

21.9

JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 69. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion will

give unpredictable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but is provided on all processors built on Power Architecture™ technology.

The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does

not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state

using only the TCK and TMS signals, generally systems will assert TRST during the power-on reset flow.

Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the

common on-chip processor (COP) function.

The COP function of these processors allow a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be

merged into these signals with logic. The arrangement shown in Figure 69 allows the COP port to

independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well.

The COP interface has a standard header, shown in Figure 68, for connection to the target system, and is

based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The

connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features. An inexpensive option can be to leave

the COP header unpopulated until needed.

There is no standardized way to number the COP header; consequently, many different pin numbers have

been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others

use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as

with an IC). Regardless of the numbering, the signal placement recommended in Figure 68 is common to

all known emulators.

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