CYWUSB6953_10 datasheet(33/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 33 of 68

3. The system-wide PD (power down) signal controls several

major circuit blocks: The Flash memory module, the internal

24 MHz oscillator, the EFTB filter and the bandgap voltage

reference. These circuits transition into a zero power state.

The only operational circuits on chip are the Low Power oscil-

lator, the bandgap refresh circuit, and the supply voltage

monitor (POR/LVD) circuit.

17.2 Low Power in Sleep Mode

To achieve the lowest possible power consumption during

suspend or sleep, the following conditions are observed in

addition to considerations for the sleep timer:

■ All GPIOs are set to outputs and driven low

■ Clear P11CR[0], P10CR[0]

■ Set P10CR[1]

■ To avoid current consumption make sure ITMRCLK and

TCPCLK are not sourced by either low power 32 kHz oscillator

or 24 MHz crystal-less oscillator.

All the other blocks go to the power down mode automatically on

suspend.

The following steps are user configurable and help in reducing

the average suspend mode power consumption:

1. Configure the power supply monitor at a large regular inter-

vals, control register bits are 1,EB[7:6] (Power system sleep

duty cycle PSSDC[1:0]).

2. Configure the Low power oscillator into low power mode,

control register bit is LOPSCTR[7].

Figure 17-1. Sleep Timing

17.3 Wakeup Sequence

When asleep, the only event that can wake the system up is an

interrupt. The global interrupt enable of the CPU flag register

does not need to be set. Any unmasked interrupt wakes the

system up. It is optional for the CPU to actually take the interrupt

after the wakeup sequence. The wakeup sequence is synchro-

nized to the 32 kHz clock. This is done to sequence a startup

delay and enable the Flash memory module enough time to

power up before the CPU asserts the first read access. Another

reason for the delay is to enable the oscillator, Bandgap, and

LVD/POR circuits time to settle before actually being used in the

system. As shown in Figure 17-2. on page 34, the wakeup

sequence is as follows:

1. The wakeup interrupt occurs and is synchronized by the

negative edge of the 32 kHz clock.

2. At the following positive edge of the 32 kHz clock, the

system-wide PD signal is negated. The Flash memory

module, internal oscillator, EFTB, and bandgap circuit are all

powered up to a normal operating state.

3. At the following positive edge of the 32 kHz clock, the current

values for the precision POR and LVD have settled and are

sampled.

4. At the following negative edge of the 32 kHz clock (after about

15 µs nominal), the BRQ signal is negated by the sleep logic

circuit. On the following CPUCLK, BRA is negated by the CPU

and instruction execution resumes. Note that in Figure 17-2.

on page 34 fixed function blocks, such as Flash, internal oscil-

lator, EFTB, and bandgap, have about 15 µs start up. The

wakeup times (interrupt to CPU operational) ranges from

75 µs to 105 µs.

Firmware write to SCR

SLEEP bit causes an

immediate BRQ

IOW

SLEEP

BRQ

BRA

CPUCLK

CPU captures

BRQ on next

CPUCLK edge

CPU

responds

with a BRA

On the falling edge of

CPUCLK, PD is asserted.

The 24/48 MHz system clock

is halted; the Flash and

bandgap are powered down

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