CYWUSB6953_10 datasheet(35/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 35 of 68

18. Low Voltage Detect Control

Table 18-1. Low Voltage Control Register (LVDCR) [0x1E3] [R/W]

Bit #

Field

Reserved

PORLEV[1:0]

Reserved

VM[2:0]

Read/Write

–

R/W

–R/W

R/W

Default

This register controls the configuration of the Power on Reset/Low voltage Detection circuit. This register can only be accessed

in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register.

Bits 7:6

Reserved

Bits 5:4

PORLEV[1:0]

This field controls the level below which the precision power on reset (PPOR) detector generates a reset

0 0 = 2.7V Range (trip near 2.6V)

0 1 = 3V Range (trip near 2.9V)

1 0 = Reserved

1 1 = PPOR does not generate a reset, but values read from the Voltage Monitor Comparators Register (Table

18-2 on page 36) give the internal PPOR comparator state with trip point set to the 3V range setting.

Bit 3

Reserved

Bits 2:0

VM[2:0]

This field controls the level below which the low voltage-detect trips—possibly generating an interrupt and the

level at which the Flash is enabled for operation.

VM[2:0]

LVD Trip Point Typ. (V)

000

2.7

001

2.92

010

3.02

011

3.13

100

101

110

111

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