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CYRF69103

Document #: 001-07611 Rev *F

Page 38 of 68

19.2 GPIO Port Configuration

All the GPIO configuration registers have common configuration

controls. The following are the bit definitions of the GPIO

configuration registers. By default all GPIOs are configured as

inputs. To prevent the inputs from floating, the pull up resistors

are enabled. Firmware needs to configure each of the GPIOs

before use.

19.2.1 Int Enable

When set, the Int Enable bit allows the GPIO to generate

interrupts. Interrupt generate can occur regardless of whether

the pin is configured for input or output. All interrupts are edge

sensitive, however for any interrupt that is shared by multiple

sources (that is, Ports 2, 3, and 4) all inputs must be deasserted

before a new interrupt can occur.

When clear, the corresponding interrupt is disabled on the pin.

It is possible to configure GPIOs as outputs, enable the interrupt

on the pin and then to generate the interrupt by driving the

appropriate pin state. This is useful in test and may have value

in applications.

19.2.2 Int Act Low

When clear, the corresponding interrupt is active HIGH. When

set, the interrupt is active LOW. For P0.3–P0.4 Int act Low clear

causes interrupts to be active on the rising edge. Int act Low set

causes interrupts to be active on the falling edge.

19.2.3 TTL Thresh

When set, the input has TTL threshold. When clear, the input has

standard CMOS threshold.

Important Note The GPIOs default to CMOS threshold. User’s

firmware needs to configure the threshold to TTL mode if

necessary.

19.2.4 High Sink

When set, the output can sink up to 50 mA.

When clear, the output can sink up to 8 mA.

On the CY7C601xx, only the P3.7, P2.7, P0.1, and P0.0 have

50 mA sink drive capability. Other pins have 8 mA sink drive

capability.

On the CY7C602xx, only the P1.7–P1.3 have 50 mA sink drive

capability. Other pins have 8 mA sink drive capability.

19.2.5 Open Drain

When set, the output on the pin is determined by the Port Data

the pin is in high impedance state. If the corresponding bit in the

Port Data Register is clear, the pin is driven LOW.

When clear, the output is driven LOW or HIGH.

19.2.6 Pull up Enable

When set the pin has a 7K pull up to VDD.

When clear, the pull up is disabled.

19.2.7 Output Enable

When set, the output driver of the pin is enabled.

When clear, the output driver of the pin is disabled.

For pins with shared functions there are some special cases.

P0.0 (CLKIN) and P0.1 (CLKOUT) can not be output enabled

when the crystal oscillator is enabled. Output enables for these

pins are overridden by XOSC Enable.

P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6 (SMISO)

can be used for their dedicated functions or for GPIO. To enable

the pin for GPIO use, clear the corresponding SPI Use bit or the

Output Enable has no effect.

19.2.8 SPI Use

The P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6

(SMISO) pins can be used for their dedicated functions or for

GPIO. To enable the pin for GPIO, clear the corresponding SPI

Use bit. The SPI function controls the output enable for its

dedicated function pins when their GPIO enable bit is clear.

Table 19-4. P0.1 Configuration (P01CR) [0x06] R/W]

Bit #

Field

Reserved

Int Enable

Int Act Low

TTL Thresh

High Sink

Open Drain

Pull up

Enable

Output

Enable

Read/Write

R/W

Default

This register is used to configure P0.1. In the CYRF69103, only 8 mA sink drive capability is available on this pin regardless of

the setting of the High Sink bit.

If this pin is used as a general purpose output it draws current. This pin must be configured as an input to reduce current draw.

Bit 7

Reserved

Bit 6

see Section 19.2.1

Bit 5

see Section 19.2.2

Bit 4

see Section 19.2.3

Bit 3

see Section 19.2.4

Bit 2

see Section 19.2.5

Bit 1

see Section 19.2.6

Bit 0

see Section 19.2.7

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