CYWUSB6953_10 datasheet(41/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 41 of 68

Table 19-9. P1.2 Configuration (P12CR) [0x0F] [R/W]

Bit #

Field

CLK Output

Int Enable

Int Act Low

TTL

Threshold

Reserved

Open Drain

Pull up

Enable

Output

Enable

Read/Write

R/W

–R/W

R/W

Default

This register controls the operation of the P1.2.

Bit 7

CLK Output

0 = The internally selected clock is not sent out onto P1.2 pin.

1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin.

Bit 6

see Section 19.2.1

Bit 5

see Section 19.2.2

Bit 4

Reserved

Bit 3

see Section 19.2.4

Bit 2

see Section 19.2.5

Bit 1

see Section 19.2.6

Bit 0

see Section 19.2.7

Table 19-10. P1.3 Configuration (P13CR) [0x10] [R/W]

Bit #

Field

Reserved

Int Enable

Int Act Low

Reserved

High Sink

Open Drain

Pull up

Enable

Output

Enable

Read/Write

–

R/W

–R/W

R/W

Default

000

This register controls the operation of the P1.3 pin.

The P1.3 GPIO’s threshold is always set to TTL.

When the SPI hardware is enabled, the output enable and output state of the pin is controlled by the SPI circuitry. When the SPI

hardware is disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register.

Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, High Sink, Open Drain, and Pull up

Enable control the behavior of the pin.

50 mA sink drive capability is available.

Bit 7

Reserved

Bit 6

see Section 19.2.1

Bit 5

see Section 19.2.2

Bit 4

Reserved

Bit 3

see Section 19.2.4

Bit 2

see Section 19.2.5

Bit 1

see Section 19.2.6

Bit 0

see Section 19.2.7

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