CYWUSB6953_10 datasheet(36/68 Pages) CYPRESS

36 / 68 page

CYRF69103

Document #: 001-07611 Rev *F

Page 36 of 68

18.1 POR Compare State

18.2 ECO Trim Register

Table 18-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]

Bit #

Field

Reserved

LVD

PPOR

Read/Write

–

––

Default

This read-only register allows reading the current state of the Low voltage Detection and Precision-Power-On-Reset

comparators:

Bits 7:2

Reserved

Bit 1

LVD

This bit is set to indicate that the low voltage detect comparator has tripped, indicating that the supply voltage has

gone below the trip point set by VM[2:0] (see Table 18-1 on page 35).

0 = No low voltage detect event

1 = A low voltage detect has tripped

Bit 0

PPOR

This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply

voltage is below the trip point set by PORLEV[1:0]:

0 = No precision-power-on-reset event

1 = A precision-power-on-reset event has tripped

Note This register can only be accessed in the second bank of I/O space. This requires setting the XIO bit in the CPU flags

Table 18-3. ECO (ECO_TR) [0x1EB] [R/W]

Bit #

Field

Sleep Duty Cycle [1:0]

Reserved

Read/Write

R/W

–

Default

This register controls the ratios (in numbers of 32 kHz clock periods) of ‘on’ time versus ‘off’ time for LVD and POR detection

circuit.

Bits 7:6

Sleep Duty Cycle [1:0]

0 0 = 1/128 periods of the Internal 32 kHz Low-speed Oscillator

0 1 = 1/512 periods of the Internal 32 kHz Low-speed Oscillator

1 0 = 1/32 periods of the Internal 32 kHz Low-speed Oscillator

1 1 = 1/8 periods of the Internal 32 kHz Low speed Oscillator

Note This register can only be accessed in the second bank of I/O space. This requires setting the XIO bit in the CPU flags

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