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CYWUSB6953 数据表(PDF) 55 Page - Cypress Semiconductor |
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CYWUSB6953 数据表(HTML) 55 Page - Cypress Semiconductor |
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55 / 68 page  CYRF69103 Document #: 001-07611 Rev *F Page 55 of 68 21.3.3 Interrupt Vector Clear Register Table 21-9. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Pending Interrupt [7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 00 0 0 The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and when written clears all pending interrupts. Bits 7:0 Pending Interrupt [7:0] 8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register clears all pending interrupts. 21.4 Microcontroller Function Register Summary Addr Name 7 6 5 4 3 2 1 0 R/W Default 00 P0DATA P0.7 Reserved Reserved P0.4/INT2 P0.3/INT1 Reserved P0.1 Reserved b--bb-b- 00000000 01 P1DATA P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 P1.1 P1.0 bbbbbbb- 00000000 02 P2DATA Reserved P2.1–P2.0 ------bb 00000000 06 P01CR Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull up Enable Output Enable bbbbbbbb 00000000 08–09 P03CR– P04CR Reserved Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable --bb-bbb 00000000 0C P07CR Reserved Int Enable Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable -bbb-bbb 00000000 0D P10CR Reserved Int Enable Int Act Low Reserved 5K pullup Enable Output enable bbb----b 00000000 0E P11CR Reserved Int Enable Int Act Low Reserved Open Drain Reserved Output Enable -bb--b-b 00000000 0F P12CR CLK Output Int Enable Int Act Low TTL Threshold Reserved Open Drain Pull up Enable Output Enable bbbb-bbb 00000000 10 P13CR Reserved Int Enable Int Act Low Reserved High Sink Open Drain Pull up Enable Output Enable -bb-bbbb 00000000 11–13 P14CR– P16CR SPI Use Int Enable Int Act Low Reserved High Sink Open Drain Pull up Enable Output Enable bbb-bbbb 00000000 14 P17CR Reserved Int Enable Int Act Low Reserved High Sink Open Drain Pull up Enable Output Enable -bb-bbbb 00000000 15 P2CR Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull up Enable Output Enable -bbbbbbb 00000000 20 FRTMRL Free Running Timer [7:0] bbbbbbbb 00000000 21 FRTMRH Free Running Timer [15:8] bbbbbbbb 00000000 26 PITMRL Prog Interval Timer [7:0] rrrrrrrr 00000000 27 PITMRH Reserved Prog Interval Timer [11:8] ----rrrr 00000000 28 PIRL Prog Interval [7:0] bbbbbbbb 00000000 29 PIRH Reserved Prog Interval [11:8] ----rrrr 00000000 30 CPUCLKCR Reserved -------- 00000000 31 TMRCLKCR TCAPCLK Divider TCAPCLK Select ITMRCLK Divider ITMRCLK Select bbbbbbbb 10001111 34 IOSCTR foffset[2:0] Gain[4:0] bbbbbbbb 000ddddd 36 LPOSCTR 32 kHz Low Power Reserved 32 kHz Bias Trim [1:0] 32 kHz Freq Trim [3:0] 0-bbbbbb d-dddddd 3C SPIDATA SPIData[7:0] bbbbbbbb 00000000 3D SPICR Swap LSB First Comm Mode CPOL CPHA SCLK Select bbbbbbbb 00000000 DA INT_CLR0 GPIO Port 1 Sleep Timer INT1 GPIO Port 0 SPI Receive SPI Transmit Reserved POR/LVD bbbbbb-b 00000000 DB INT_CLR1 Reserved Prog Interval Timer 1 ms Timer Reserved -bb----- 00000000 DC INT_CLR2 Reserved Reserved Reserved GPIO Port 2 Reserved INT2 16-bit Counter Wrap Reserved ---b-bb- 00000000 [+] Feedback |
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