CYRF69103

Document #: 001-07611 Rev *F

Page 57 of 68

22. Radio Function Register Summary

All registers are read and writable, except where noted. Registers may be written to or read from either individually or in sequential

groups. A single-byte read or write reads or writes from the addressed register. Incrementing burst read and write is a sequence that

begins with an address, and then reads or writes to/from each register in address order for as long as clocking continues. It is possible

to repeatedly read (poll) a single register using a nonincrementing burst read.

Notes

4. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.

5. SOP_CODE_ADR default = 0x17FF9E213690C782.

6. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.

7. PREAMBLE_ADR default = 0x333302;The count value must be great than 4 for DDR and greater than 8 for SDR

8. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode.The PMU, GPIOs, RSSI registers can be accessed in Active Tx and Rx mode.

9. EOP_CTRL_ADR[6:4] must never have the value of “000” i.e. EOP Hint Symbol count must never be “0”

10. PFET Bit: Setting this bit to "1" disables the FET, therefore safely allowing Vbat to be connected to a separate reference from Vcc when the PMU is disabled to the radio.om Vcc when the

PMU is disabled to the radio.

Address

Mnemonic

b7

b6

b5

b4

b3

b2

b1

b0

Default[4]

Access[4]

0x00

CHANNEL_ADR

Not Used

Channel

-1001000

-bbbbbbb

0x01

TX_LENGTH_ADR

TX Length

00000000

bbbbbbbb

0x02

TX_CTRL_ADR

TX GO

TX CLR

TXB15

IRQEN

TXB8

IRQEN

TXB0

IRQEN

TXBERR

IRQEN

TXC

IRQEN

TXE

IRQEN

00000011

bbbbbbbb

0x03

TX_CFG_ADR

Not Used

Not Used

DATA CODE

LENGTH

DATA MODE

PA SETTING

--000101

--bbbbbb

0x04

TX_IRQ_STATUS_ADR

OS

IRQ

LV

IRQ

TXB15

IRQ

TXB8

IRQ

TXB0

IRQ

TXBERR

IRQ

TXC

IRQ

TXE

IRQ

--------

rrrrrrrr

0x05

RX_CTRL_ADR

RX GO

RSVD

RXB16

IRQEN

RXB8

IRQEN

RXB1

IRQEN

RXBERR

IRQEN

RXC

IRQEN

RXE

IRQEN

00000111

bbbbbbbb

0x06

RX_CFG_ADR

AGC EN

LNA

ATT

HILO

FASTTURN

EN

Not Used

RXOW EN

VLD EN

10010-10

bbbbb-bb

0x07

RX_IRQ_STATUS_ADR

RXOW

IRQ

SOPDET

IRQ

RXB16

IRQ

RXB8

IRQ

RXB1

IRQ

RXBERR

IRQ

RXC

IRQ

RXE

IRQ

--------

brrrrrrr

0x08

RX_STATUS_ADR

RX ACK

PKT ERR

EOP ERR

CRC0

Bad CRC

RX Code

RX Data Mode

--------

rrrrrrrr

0x09

RX_COUNT_ADR

RX Count

00000000

rrrrrrrr

0x0A

RX_LENGTH_ADR

RX Length

00000000

rrrrrrrr

0x0B

PWR_CTRL_ADR

PMU EN

LVIRQ EN

PMU Mode

Force

PFET

disable

[10.]

LVI TH

PMU OUTV

10100000

bbb-bbbb

0x0C

XTAL_CTRL_ADR

XOUT FN

XSIRQ EN

Not Used

Not Used

FREQ

000--100

bbb--bbb

0x0D

IO_CFG_ADR

IRQ OD

IRQ POL

MISO OD

XOUT OD

PACTL OD PACTL GPIO

SPI 3PIN

IRQ GPIO

00000000

bbbbbbbb

0x0E

GPIO_CTRL_ADR

XOUT OP

MISO OP

PACTL OP

IRQ OP

XOUT IP

MISO IP

PACTL IP

IRQ IP

0000----

bbbbrrrr

0x0F

XACT_CFG_ADR

ACK EN

Not Used

FRC END

END STATE

ACK TO

1-000000

b-bbbbbb

0x10

FRAMING_CFG_ADR

SOP EN

SOP LEN

LEN EN

SOP TH

10100101

bbbbbbbb

0x11

DATA32_THOLD_ADR

Not Used

Not Used

Not Used

Not Used

TH32

----0100

----bbbb

0x12

DATA64_THOLD_ADR

Not Used

Not Used

Not Used

TH64

---01010

---bbbbb

0x13

RSSI_ADR

SOP

Not Used

LNA

RSSI

0-100000

r-rrrrrr

0x14

EOP_CTRL_ADR [9.]

HEN

HINT

EOP

10100100

bbbbbbbb

0x15

CRC_SEED_LSB_ADR

CRC SEED LSB

00000000

bbbbbbbb

0x16

CRC_SEED_MSB_ADR

CRC SEED MSB

00000000

bbbbbbbb

0x17

TX_CRC_LSB_ADR

CRC LSB

--------

rrrrrrrr

0x18

TX_CRC_MSB_ADR

CRC MSB

--------

rrrrrrrr

0x19

RX_CRC_LSB_ADR

CRC LSB

11111111

rrrrrrrr

0x1A

RX_CRC_MSB_ADR

CRC MSB

11111111

rrrrrrrr

0x1B

TX_OFFSET_LSB_ADR

STRIM LSB

00000000

bbbbbbbb

0x1C

TX_OFFSET_MSB_ADR

Not Used

Not Used

Not Used

Not Used

STRIM MSB

----0000

----bbbb

0x1D

MODE_OVERRIDE_ADR

RSVD

RSVD

FRC SEN

FRC AWAKE

Not Used

Not Used

RST

00000--0

wwwww--w

0x1E

RX_OVERRIDE_ADR

ACK RX

RXTX DLY

MAN RXACK

FRC

RXDR

DIS CRC0

DIS RXCRC

ACE

Not Used

0000000-

bbbbbbb-

0x1F

TX_OVERRIDE_ADR

ACK TX

FRC PRE

RSVD

MAN

TXACK

OVRD ACK DIS TXCRC

RSVD

TX INV

00000000

bbbbbbbb

0x26

XTAL_CFG_ADR

RSVD

RSVD

RSVD

RSVD

START DLY

RSVD

RSVD

RSVD

00000000

wwwwwww

w

0x27

CLK_OVERRIDE_ADR

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RXF

RSVD

00000000

wwwwwww

w

0x28

CLK_EN_ADR

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RXF

RSVD

00000000

wwwwwww

w

0x29

RX_ABORT_ADR

RSVD

RSVD

ABORT EN

RSVD

RSVD

RSVD

RSVD

RSVD

00000000

wwwwwww

w

0x32

AUTO_CAL_TIME_ADR

AUTO_CAL_TIME

00000011

wwwwwww

w

0x35

AUTO_CAL_OFFSET_ADR

AUTO_CAL_OFFSET

00000000

wwwwwww

w

0x39

ANALOG_CTRL_ADR

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RX INV

ALL SLOW

00000000

wwwwwww

w

Register Files

0x20

TX_BUFFER_ADR

TX Buffer File

--------

wwwwwww

w

0x21

RX_BUFFER_ADR

RX Buffer File

--------

rrrrrrrr

0x22

SOP_CODE_ADR

SOP Code File

Note [5]

bbbbbbbb

0x23

DATA_CODE_ADR

Data Code File

Note [6]

bbbbbbbb

0x24

PREAMBLE_ADR

Preamble File

Note [7]

bbbbbbbb

0x25

MFG_ID_ADR

MFG ID File

NA

rrrrrrrr

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