CYWUSB6953_10 datasheet(53/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 53 of 68

Table 21-5. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]

Bit #

Field

ENSWINT

Reserved

Read/Write

–

Default

Bit 7

Enable Software Interrupt (ENSWINT)

0 = Disable. Writing 0's to an INT_CLRx register, when ENSWINT is cleared, cause the corresponding interrupt to

clear

1 = Enable. Writing 1's to an INT_CLRx register, when ENSWINT is set, cause the corresponding interrupt to post

Bits 6:0

Reserved

Table 21-6. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]

Bit #

Field

Reserved

GPIO Port 2

Int Enable

Reserved

INT2

Int Enable

16-bit

Counter

Wrap Int

Enable

Reserved

Read/Write

–

R/W

–R/W

R/W

Default

Bit 7:

Reserved

Bit 6:

Reserved

Bit 5:

Reserved

Bit 4:

GPIO Port 2 Interrupt Enable

0 = Mask GPIO Port 2 interrupt

1 = Unmask GPIO Port 2 interrupt

Bit 3:

Reserved

Bit 2:

INT2 Interrupt Enable

0 = Mask INT2 interrupt

1 = Unmask INT2 interrupt

Bit 1:

16-bit Counter Wrap Interrupt Enable

0 = Mask 16-bit Counter Wrap interrupt

1 = Unmask 16-bit Counter Wrap interrupt

Bit 0:

Reserved

The GPIO interrupts are edge-triggered.

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