CYWUSB6953_10 datasheet(60/68 Pages) CYPRESS

60 / 68 page

CYRF69103

Document #: 001-07611 Rev *F

Page 60 of 68

Figure 25-1. Clock Timing

Note

18. In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.

25. AC Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

GPIO Timing

TR_GPIO

Output Rise Time

Measured between 10 and 90%

Vdd/Vreg with 50 pF load

TF_GPIO

Output Fall Time

Measured between 10 and 90%

Vdd/Vreg with 50 pF load

FIMO

Internal Main Oscillator Frequency

With proper trim values loaded[5]

18.72

26.4

MHz

FILO

Internal Low Power Oscillator

With proper trim values loaded[5]

15.0001

50.0

kHz

SPI Timing

TSMCK

SPI Master Clock Rate

FCPUCLK/6

MHz

TSSCK

SPI Slave Clock Rate

2.2

MHz

TSCKH

SPI Clock High Time

High for CPOL = 0, Low for CPOL = 1

125

TSCKL

SPI Clock Low Time

Low for CPOL = 0, High for CPOL = 1

125

TMDO

Master Data Output Time[18]

SCK to data valid

–25

TMDO1

Master Data Output Time,

First bit with CPHA = 0

Time before leading SCK edge

100

TMSU

Master Input Data Setup time

TMHD

Master Input Data Hold time

TSSU

Slave Input Data Setup Time

TSHD

Slave Input Data Hold Time

TSDO

Slave Data Output Time

SCK to data valid

100

TSDO1

Slave Data Output Time,

First bit with CPHA = 0

Time after SS LOW to data valid

100

TSSS

Slave Select Setup Time

Before first SCK edge

150

TSSH

Slave Select Hold Time

After last SCK edge

150

CLOCK

TCYC

TCL

TCH

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