CYWUSB6953_10 datasheet(12/68 Pages) CYPRESS

12 / 68 page

CYRF69103

Document #: 001-07611 Rev *F

Page 12 of 68

9.3 SPI Communication and Transactions

The SPI transactions can be single byte or multi-byte. The MCU

function initiates a data transfer through a Command/Address

byte. The following bytes are data bytes. The SPI transaction

format is shown in Figure 9-1.

The DIR bit specifies the direction of data transfer. 0 = Master

reads from slave. 1 = Master writes to slave.

The INC bit helps to read or write consecutive bytes from

contiguous memory locations in a single burst mode operation.

If Slave Select is asserted and INC = 1, then the master MCU

function reads a byte from the radio, the address is incremented

by a byte location, and then the byte at that location is read, and

so on.

If Slave Select is asserted and INC = 0, then the MCU function

reads/writes the bytes in the same register in burst mode, but if

it is a register file then it reads/writes the bytes in that register file.

The SPI interface between the radio function and the MCU is not

dependent on the internal 12 MHz oscillator of the radio.

Therefore, radio function registers can be read from or written

into while the radio is in sleep mode.

9.4 SPI I/O Voltage References

The SPI interfaces between MCU function and the radio and the

IRQ and RST have a separate voltage reference VIO. For

CYRF69103 VIO is normally set to VCC.

9.5 SPI Connects to External Devices

The three SPI wires, MOSI, SCK, and SS are also drawn out of

the package as external pins to allow the user to interface their

own external devices (such as optical sensors and others)

through SPI. The radio function also has its own SPI wires MISO

and IRQ, which can be used to send data back to the MCU

function or send an interrupt request to the MCU function. They

can also be configured as GPIO pins.

10. CPU Architecture

This family of microcontrollers is based on a high-performance,

8-bit, Harvard architecture microprocessor. Five registers control

the primary operation of the CPU core. These registers are

affected by various instructions, but are not directly accessible

through the register space by the user.

The 16-bit Program Counter Register (CPU_PC) allows for direct

addressing of the full eight Kbytes of program memory space.

The Accumulator Register (CPU_A) is the general-purpose

the source addressing modes.

The Index Register (CPU_X) holds an offset value that is used

in the indexed addressing modes. Typically, this is used to

address a block of data within the data memory space.

The Stack Pointer Register (CPU_SP) holds the address of the

current top-of-stack in the data memory space. It is affected by

the PUSH, POP, LCALL, CALL, RETI, and RET instructions,

which manage the software stack. It can also be affected by the

SWAP and ADD instructions.

The Flag Register (CPU_F) has three status bits: Zero Flag bit

[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global

Interrupt Enable bit [0] is used to globally enable or disable inter-

rupts. The user cannot manipulate the Supervisory State status

bit [3]. The flags are affected by arithmetic, logic, and shift opera-

tions. The manner in which each flag is changed is dependent

upon the instruction being executed (for example, AND, OR,

XOR). See Table 13-1 on page 18.

Table 9-1. SPI Transaction Format

Byte 1

Byte 1+N

Bit #

[5:0]

[7:0]

Bit Name

DIR

INC

Address

Data

Table 10-1. CPU Registers and Register Name

Flags

CPU_F

Program Counter

CPU_PC

Accumulator

CPU_A

Stack Pointer

CPU_SP

Index

CPU_X

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