CYWUSB6953_10 datasheet(32/68 Pages) CYPRESS

32 / 68 page

CYRF69103

Document #: 001-07611 Rev *F

Page 32 of 68

16.1 Power On Reset

POR occurs every time the power to the device is switched on.

POR is released when the supply is typically 2.6V for the upward

supply transition, with typically 50 mV of hysteresis during the

power on transient. Bit 4 of the System Status and Control

contents are set to 00010000 by the POR). After a POR, the

microprocessor is held off for approximately 20 ms for the VCC

supply to stabilize before executing the first instruction at

address 0x00 in the Flash. If the VCC voltage drops below the

POR downward supply trip point, POR is reasserted. The VCC

supply needs to ramp linearly from 0 to VCC in 0 to 200 ms.

Important The PORS status bit is set at POR and can only be

cleared by the user, and cannot be set by firmware.

16.2 Watchdog Timer Reset

The user has the option to enable the WDT. The WDT is enabled

by clearing the PORS bit. When the PORS bit is cleared, the

WDT cannot be disabled. The only exception to this is if a POR

event takes place, which disables the WDT.

The sleep timer is used to generate the sleep time period and the

Watchdog time period. The sleep timer uses the Internal 32 kHz

Low power Oscillator system clock to produce the sleep time

period. The user can program the sleep time period using the

Sleep Timer bits of the OSC_CR0 Register (Table 15-3). When

the sleep time elapses (sleep timer overflows), an interrupt to the

Sleep Timer Interrupt Vector is generated.

The Watchdog Timer period is automatically set to be three

counts of the Sleep Timer overflows. This represents between

two and three sleep intervals depending on the count in the

Sleep Timer at the previous WDT clear. When this timer reaches

three, a WDR is generated.

The user can either clear the WDT, or the WDT and the Sleep

Timer. Whenever the user writes to the Reset WDT Register

(RES_WDT), the WDT is cleared. If the data that is written is the

hex value 0x38, the Sleep Timer is also cleared at the same time.

17. Sleep Mode

The CPU can only be put to sleep by the firmware. This is accom-

plished by setting the Sleep bit in the System Status and Control

instructions, and the CPU remains asleep until an interrupt

comes pending, or there is a reset event (either a Power on

Reset, or a Watchdog Timer Reset).

The Low voltage Detection circuit (LVD) drops into fully functional

power reduced states, and the latency for the LVD is increased.

The actual latency can be traded against power consumption by

changing the Sleep Duty Cycle field of the ECO_TR Register.

The Internal 32 kHz low speed oscillator remains running. Before

entering suspend mode, firmware can optionally configure the 32

kHz Low speed Oscillator to operate in a low power mode to help

reduce the overall power consumption (using the 32 kHz Low

Power bit, Table 15-6). This helps save approximately 5

μA;

however, the trade off is that the 32 kHz Low speed Oscillator be

less accurate (–53.12% to +56.25% deviation).

All interrupts remain active. Only the occurrence of an interrupt

wakes the part from sleep. The Stop bit in the System Status and

Control Register (CPU_SCR) must be cleared for a part to

resume out of sleep. The Global Interrupt Enable bit of the CPU

Flags Register (CPU_F) does not have any effect. Any

unmasked interrupt wakes the system up. As a result, any inter-

rupts not intended for waking must be disabled through the

Interrupt Mask Registers.

When the CPU enters sleep mode, the internal oscillator is

stopped. When the CPU comes out of sleep mode, it is running

on the internal oscillator. The internal oscillator recovery time is

three clock cycles of the Internal 32 kHz Low power Oscillator.

On exiting sleep mode, when the clock is stable and the delay

time has expired, the instruction immediately following the sleep

instruction is executed before the interrupt service routine (if

enabled).

The Sleep interrupt allows the microcontroller to wake up period-

ically and poll system components while maintaining very low

average power consumption. The Sleep interrupt may also be

used to provide periodic interrupts during non sleep modes.

17.1 Sleep Sequence

The Sleep bit is an input into the sleep logic circuit. This circuit is

designed to sequence the device into and out of the hardware

sleep state. The hardware sequence to put the device to sleep

is shown in Figure 17-1. on page 33 and is defined as follows.

1. Firmware sets the SLEEP bit in the CPU_SCR0 register. The

Bus Request (BRQ) signal to the CPU is immediately assert-

ed. This is a request by the system to halt CPU operation at

an instruction boundary. The CPU samples BRQ on the pos-

itive edge of CPUCLK.

2. Due to the specific timing of the register write, the CPU issues

a Bus Request Acknowledge (BRA) on the following positive

edge of the CPU clock. The sleep logic waits for the following

negative edge of the CPU clock and then asserts a

system-wide Power Down (PD) signal. In Figure 17-1. on

page 33 the CPU is halted and the system-wide power down

signal is asserted.

Table 16-2. Reset Watchdog Timer (RESWDT) [0xE3] [W]

Bit #

Field

Reset Watchdog Timer [7:0]

Read/Write

Default

Any write to this register clears the Watchdog Timer, a write of 0x38 also clears the Sleep Timer.

Bits 7:0

Reset Watchdog Timer [7:0]

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