CYWUSB6953_10 datasheet(43/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 43 of 68

19.3 GPIO Configurations for Low Power Mode

To ensure low power mode, unbonded GPIO pins in CYRF69103 must be placed in a non-floating state. The following assembly code

snippet shows how this is achieved. This snippet can be added as a part of the initialization routine.

//Code Snippet for addressing unbonded GPIOs

mov A, 01h

mov reg[1Fh],A

mov A, 01h

mov reg[16h],A // Port3 Configuration register - Enable output

mov A, 00h

mov reg[03h],A // Asserting P3.0 to P3.7 outputs to '0'

//Port 2 configurations

mov A,01h

mov reg[15h],A //Port 2 Configuration register -Enable output

mov A,00h

mov reg[02h],A //Asserting P2.0 to P2.7 outputs to ‘0’

mov A, 01h

mov reg[05h],A // Port0.0 Configuration register - Enable output

mov reg[07h],A // Port0.2 Configuration register - Enable output

mov reg[0Ah],A // Port0.5 Configuration register - Enable output

mov reg[0Bh],A // Port0.6 Configuration register - Enable output

mov A,reg[00h]

mov A,00h

and A,9Ah

mov reg[00h], A // Asserting outputs '0' to pins in port 1

// NOTE: The code fragment in italics is to be used only if your application configures P2.0 and

P2.1 as push-pull outputs.

When writing to port 0, to access GPIOs P0.1,3,4,7, mask bits 0,2,5,6. Failing to do so voids the low power.

Table 19-13. P2 Configuration (P2CR) [0x15] [R/W]

Bit #

Field

Reserved

Int Enable

Int Act Low

TTL Thresh

High Sink

Open Drain

Pull up

Enable

Output

Enable

Read/Write

–

R/W

Default

0000000

This register controls the operation of pins P2.0–P2.1.

Bit 7

Reserved

Bit 6

see Section 19.2.1

Bit 5

see Section 19.2.2

Bit 4

see Section 19.2.3

Bit 3

see Section 19.2.4

Bit 2

see Section 19.2.5

Bit 1

see Section 19.2.6

Bit 0

see Section 19.2.7

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