CYWUSB6953_10 datasheet(51/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 51 of 68

Figure 21-1. Interrupt Controller Block Diagram

21.1 Interrupt Processing

The sequence of events that occur during interrupt processing is

as follows:

1. An interrupt becomes active, either because:

a. The interrupt condition occurs (for example, a timer expires).

b. A previously posted interrupt is enabled through an update

of an interrupt mask register.

c. An interrupt is pending and GIE is set from 0 to 1 in the CPU

Flag register.

2. The current executing instruction finishes.

3. The internal interrupt is dispatched, taking 13 cycles. During

this time, the following actions occur:

a. The MSB and LSB of Program Counter and Flag registers

(CPU_PC and CPU_F) are stored onto the program stack

by an automatic CALL instruction (13 cycles) generated

during the interrupt acknowledge process.

b. The PCH, PCL, and Flag register (CPU_F) are stored onto

the program stack (in that order) by an automatic CALL

instruction (13 cycles) generated during the interrupt

acknowledge process.

c. The CPU_F register is then cleared. Because this clears the

GIE bit to 0, additional interrupts are temporarily disabled.

d. The PCH (PC[15:8]) is cleared to zero.

e. The interrupt vector is read from the interrupt controller and

its value placed into PCL (PC[7:0]). This sets the program

counter to point to the appropriate address in the interrupt

table (for example, 0004h for the POR/LVD interrupt).

4. Program execution vectors to the interrupt table. Typically, a

LJMP instruction in the interrupt table sends execution to the

user's Interrupt Service Routine (ISR) for this interrupt.

5. The ISR executes. Note that interrupts are disabled because

GIE = 0. In the ISR, interrupts can be re-enabled if desired by

setting GIE = 1 (care must be taken to avoid stack overflow).

6. The ISR ends with a RETI instruction which restores the

Program Counter and Flag registers (CPU_PC and CPU_F).

The restored Flag register re-enables interrupts because GIE

= 1 again.

7. Execution resumes at the next instruction, after the one that

occurred before the interrupt. However, if there are more

pending interrupts, the subsequent interrupts are processed

before the next normal program instruction.

21.2 Interrupt Latency

The time between the assertion of an enabled interrupt and the

start of its ISR can be calculated from the following equation.

Latency = Time for current instruction to finish + Time for internal

interrupt routine to execute + Time for LJMP instruction in

interrupt table to execute.

For example, if the 5-cycle JMP instruction is executing when an

interrupt becomes active, the total number of CPU clock cycles

before the ISR begins is as follows:

(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine)

+ (7 cycles for LJMP) = 21 to 25 cycles.

In the following example, at 12 MHz, 25 clock cycles take

2.08 µs.

21.3 Interrupt Registers

The Interrupt Registers are discussed it the following sections.

21.3.1 Interrupt Clear Register

The Interrupt Clear Registers (INT_CLRx) are used to enable the

individual interrupt sources’ ability to clear posted interrupts.

When an INT_CLRx register is read, any bits that are set

indicates an interrupt has been posted for that hardware

resource. Therefore, reading these registers gives the user the

ability to determine all posted interrupts.

Interrupt

Source

(Timer,

GPIO,etc.)

InterruptTaken

Posted

Interrupt

Pending

Interrupt

GIE

Interrupt Vector

Mask Bit Setting

Priority

Encoder

M8C Core

Interrupt

Request

INT_MSKx

INT_CLRxWrite

CPU_F[0]

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