CYWUSB6953_10 datasheet(27/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 27 of 68

Table 15-3. OSC Control 0 (OSC_CR0) [0x1E0] [R/W]

Bit #

Field

Reserved

No Buzz

Sleep Timer [1:0]

CPU Speed [2:0]

Read/Write

–

R/W

Default

0001000

Bits 7:6

Reserved

Bit 5

No Buzz

During sleep (the Sleep bit is set in the CPU_SCR Register—Table 16-1 on page 31), the LVD and POR detection

circuit is turned on periodically to detect any POR and LVD events on the VCC pin (the Sleep Duty Cycle bits in the

ECO_TR are used to control the duty cycle—Table 18-3 on page 36). To facilitate the detection of POR and LVD

events, the No Buzz bit is used to force the LVD and POR detection circuit to be continuously enabled during

sleep. This results in a faster response to an LVD or POR event during sleep at the expense of a slightly higher

than average sleep current. Obtaining the absolute lowest power usage in sleep mode requires the No Buzz bit be

clear

0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle.

1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled.

Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the following Sleep [1:0] bits.

Bits 4:3

Sleep Timer [1:0]

Note Sleep intervals are approximate

Bits 2:0

CPU Speed [2:0]

The CYRF69103 may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero.

Therefore, the default CPU speed is 3 MHz.

Sleep Timer

[1:0]

Sleep Timer Clock

Frequency (Nominal)

Sleep Period

(Nominal)

Watchdog Period

(Nominal)

512 Hz

1.95 ms

6 ms

64 Hz

15.6 ms

47 ms

8 Hz

125 ms

375 ms

1 Hz

1 sec

3 sec

CPU Speed

[2:0]

CPU when Internal

Oscillator is selected

000

3 MHz (Default)

001

6 MHz

010

12 MHz

011

Reserved

100

1.5 MHz

101

750 kHz

110

187 kHz

111

Reserved

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