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CYRF69103

Document #: 001-07611 Rev *F

Page 4 of 68

6.4 Backward Compatibility

The CYRF69103 IC is fully interoperable with the main modes of

the first generation Cypress radios namely the CYWUSB6934

-LS and CYWWUSB6935-LR devices. The 62.5 kbps mode is

supported by selecting 32 chip DDR mode. Similarly, the

15.675 kbps mode is supported by selecting 64 chip SDR mode

In this method, a suitably configured CYRF69103 IC device may

transmit data to or receive data from a first generation device, or

both. Backwards compatibility requires disabling the SOP,

length, and CRC16 fields.

This section provides the different configurations of the registers

and firmware that enable a new generation radio to communicate

with a first generation radio. There are two possible modes: SDR

and DDR mode (8-DR and GFSK modes are not present in the

first generation radio). The second generation radio must be

initialized using the RadioInitAPI of the LP radio driver and then

the following registers’ bits need to be configured to the given

Byte values. Essentially, the following deactivates the added

features of the second generation radio and takes it down to the

level of the first generation radio. The data format, data rates,

and the PN codes used are recognizable by the first generation

radio.

6.5 DDR Mode

Table 6-1. DDR Mode

Value

Description

TX_CFG_ADR

0X16

32 chip PN Code, DDR, PA = 6

RX_CFG_ADR

0X4B

AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the

device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive

buffer is enabled and the RX buffer is configured to receive eight bytes maximum.

XACT_CFG_ADR

0X05

AutoACK is disabled. Forcing end state is disabled. The device is configured to

transition to Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs.

FRAMING_CFG_ADR

0X00

All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed.

TX_OVERRIDE_ADR

0X04

Disable Transmit CRC-16.

RX_OVERRIDE_ADR

0X14

The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled

and the receiver accepts bad packets that do not match the seed in CRC_seed

registers. This helps in communication with the first generation radio that does not

have CRC capabilities.

ANALOG_CTRL_ADR

0X01

Set ALL SLOW. When set, the synthesizer settle time for all channels is the same

as the slow channels in the first generation radio.

DATA32_THOLD_ADR

0X03

Sets the number of allowed corrupted bits to 3.

EOP_CTRL_ADR

0x01

Sets the number of consecutive symbols for non-correlation to detect end of packet.

PREAMBLE_ADR

0xAAAA05

AAAA are the two preamble bytes. Any other byte can also be written into the

preamble register file. Recommended counts of the preamble bytes to be sent must

be >4.

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