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ST7LITE20F2 数据表(PDF) 132 Page - STMicroelectronics |
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ST7LITE20F2 数据表(HTML) 132 Page - STMicroelectronics |
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132 / 166 page ![]() Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 132/166 Doc ID 8349 Rev 5 Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. Note: For more details, refer to the application note AN1015. 13.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Note: Data based on characterization results, not tested in production. 13.7.3 Absolute maximum ratings (Electrical sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. Note: For more details, refer to the application note AN1181. Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. Table 76. Test results Symbol Parameter Conditions Level/Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-2 3B VFFTB Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-4 3B Table 77. Emission test Symbol Parameter Conditions Monitored Frequency Band Max vs. [fOSC/fCPU]Unit 8/4MHz 16/8MHz − SEMI Peak level VDD=5V, TA=+25°C, SO20 package, conforming to SAE J 1752/3 0.1 MHz to 30 MHz 9 17 dB μV 30 MHz to 130 MHz 31 36 130 MHz to 1 GHz 25 27 SAE EMI Level 3.5 4 − |
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