AX2000 datasheet(22/262 Pages) MICROSEMI

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Detailed Specifications

2- 8

R ev isio n 1 8

Timing Model

Hardwired Clock – Using LVTTL 24 mA High Slew Clock I/O

Routed Clock – Using LVTTL 24 mA High Slew Clock I/O

Note:

Worst case timing data for the AX1000, –2 speed grade

Figure 2-1 •

Worst Case Timing Data

Combinatorial

Cell

Combinatorial

Cell

Combinatorial

Cell

Combinatorial

Cell

FCO

Routed Clock

LVPECL

LVDS

Hardwired or

Routed Clock

Hardwired Clock

I/O Module

(Registered)

I/O Module

(Nonregistered)

I/O Module

(Non- registered)

I/O Module

(Nonregistered)

Buffer

Module

Buffer

Module

Buffer

Module

Carry Chain

I/O

LVTTL

Output Drive

Strength = 4 (24 mA)

High Slew Rate

tHCKH = 3.03 ns

FMAX (external) = 350 MHz

FMAX (internal) = 870 MHz

tSUD = 0.23 ns

tICKLQ = 0.67 ns

tDP = 1.66 ns

tRD2 = 0.53 ns

tDP = 1.80 ns

tHCKL = 3.02 ns

tRCKL = 3.08 ns

tRCO = 0.67 ns

tSUD = 0.23 ns

tRD1 = 0.45 ns

tPD = 0.74 ns

tRCKL = 3.08 ns

FMAX (external) = 350 MHz

FMAX (internal) = 870 MHz

tRCO = 0.67 ns

tSUD = 0.23 ns

tBPFD = 0.12 ns

tPY = 1.13 ns

GTL + 3.3 V

tIOCLKY = 0.67 ns

tSUD = 0.23 ns

tBFPD = 0.12 ns tPD = 0.74 ns tBFPD = 0.12 ns

tPDC = 0.57 ns

tCCY = 0.61 ns

tPY = 2.99 ns

tPY = 2.24 ns

tRD1 = 0.45 ns

tRD2 = 0.53 ns

tRD3 = 0.56 ns

External Setup

= (tDP + tRD2 + tSUD) – tHCKL

= (1.72 + 0.53 + 0.23) – 3.02 = –0.54 ns

Clock-to-Out (Pad-to-Pad)

= tHCKL + tRCO + tRD1 + tPY

= 3.02 + 0.67 + 0.45 + 2.99 = 7.13 ns

External Setup

= (tDP + tRD2 + tSUD) – tRCKH

= (1.72 + 0.53 + 0.23) – 3.13 = –0.65 ns

Clock-to-Out (Pad-to-Pad)

= tRCKH + tRCO + tRD1 + tPY

= 3.13 + 0.67 + 0.45 + 3.03 = 7.24 ns

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